Technical Field
The present invention relates to semiconductor processing, and more particularly to devices and methods for forming high concentration SiGe fins on a dielectric layer.
Description of the Related Art
Many semiconductor devices employ fin structures for the formation of the field effect transistors (finFETs). N-type field effect transistors (NFETs) are formed in silicon and P-type field effect transistors (PFETs) are formed in SiGe material.
In some instances, the use of SiGe fins is advantageous due to improved mobility; however, SiGe structures formed epitaxially may be limited by critical thickness. For example, if the thickness of the epitaxial layer is kept small enough to maintain its elastic strain energy below an energy of dislocation formation (defects), the strained-layer structure will be thermodynamically stable against dislocation formation. To maintain a defect free epitaxial layer, the thickness of the layer is limited.
In conventional fin formation processes, Ge condensation is employed to provide high concentration Ge in SiGe fins. A bulk silicon substrate is etched to form fins and SiGe cladding is grown on fin regions exposed through a shallow trench isolation (STI) layer. The SiGe cladding is faceted in shape. The SiGe is then buried in oxide and annealed at high temperatures (e.g., 900-1000 degrees C.) to drive in the Ge into the fins from the cladding. The annealing may be performed in multiple cycles.
The fin profile (shape) is affected by the annealing process and the faceted SiGe cladding epitaxial morphology. In addition, the Ge diffusion into the fin channel region/substrate and punch through stopper (PTS) dopant (e.g., As/P) diffusion into the fin channel region due to high thermal budget may impact mobility in the fin channel.